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UC2842/3/4/5 UC3842/3/4/5
CURRENT MODE PWM CONTROLLER
.OPTI .LOWSTART.AUTOMATI .PULSE.ENHANCED .UNDER.DOUBLEPULSESUPPRESSI .HI .I .500KHzOPERATI .LOWROERRORAMP
DESCRIPTION
MIZED FOR OFF-LINE AND DC TO DC CONVERTERS UP CURRENT (< 1 mA) C FEED FORWARD COMPENSATION BY-PULSE CURRENT LIMITING LOAD RESPONSE CHARACTERISTICS VOLTAGE LOCKOUT WITH HYSTERESIS ON GH CURRENT TOTEM POLE OUTPUT NTERNALLY TRIMMED BANDGAP REFERENCE ON
Minidip
SO14
TheUC3842/3/4/5family of controlICs provides the necessary features to implement off-line or DC to DC fixed frequency current mode control schemes with a minimal externalparts count.Internallyimplementedcircuits include undervoltagelockout featuring start-up current less than 1 mA, a precision reference trimmed for accuracy at the error amp input,
logic to insure latched operation, a PWM comparatorwhich also providescurrentlimit control,and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in theoff-state. Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC3842 and UC3844 have UVLO thresholds of 16V (on) and 10V (off), ideally suited off-line applications The corresponding thresholds for the UC3843 and UC3845 are 8.5 V and 7.9 V. The UC3842 and UC3843 can operate to duty cycles approaching 100%. A range of the zero to < 50 % is obtained by the UC3844 and UC3845 by the additionof an internal toggle flip flop which blanks the output off every other clock cycle.
BLOCK DIAGRAM (toggle flip flop used only in U3844 and UC3845)
October 1998
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ABSOLUTE MAXIMUM RATINGS
Symbol Vi Vi IO EO Parameter Supply Voltage (low impedance source) Supply Voltage (Ii < 30mA) Output Current Output Energy (capacitive load) Analog Inputs (pins 2, 3) Error Amplifier Output Sink Current Ptot Ptot Tstg TL Power Dissipation at Tamb 50 C (minidip, DIP-14) Power Dissipation at Tamb 25 C (SO14) Storage Temperature Range Lead Temperature (soldering 10s) Value 30 Self Limiting 1 5 - 0.3 to 6.3 10 1 725 - 65 to 150 300 A J V mA W mW C C Unit V
* All voltages are with respect to pin 5, all currents are positive into the specified terminal.
PIN CONNECTIONS (top views) SO14 Minidip
ORDERING NUMBERS
T ype UC2842 UC3843 UC2844 UC2845 UC3842 UC3843 UC3844 UC3845 Min idip UC2842N UC2843N UC2844N UC2845N UC3842N UC3843N UC3844N UC3845N SO14 UC2842D UC2843D UC2844D UC2845D UC3842D UC3843D UC3844D UC3845D
THERMAL DATA
Symbol R th j-amb Description Thermal Resistance Junction-ambient. max. Min id ip 100 SO14 165 Unit C
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ELECTRICAL CHARACTERISTICS (Unless otherwise stated, these specifications apply for -25 < Tamb < 85C for UC2824X; 0 < Tamb < 70C for UC384X; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)
Symbo l Parameter T est Cond ition s REFERENCE SECTION VREF V REF V REF VREF/T eN Output Voltage Line Regulation Load Regulation Temperature Stability Total Output Variant Output Noise Voltage Long Term Stability ISC fs Output Short Circuit OSCILLATOR SECTION Initial Accuracy Voltage Stability Temperature Stability V4 V2 Ib B SVR Io Io Amplitude Input Voltage Input Bias Current AVOL Unity Gain Bandwidth Supply Voltage Rejection Output Sink Current Output Source Current VOUT High VOUT Low 2 Vo 4V (2) 12V Vi 25V VPIN2 = 2.7V VPIN1 = 1.1V VPIN2 = 2.3V VPIN1 = 5V VPIN2 = 2.3V; RL = 15K to Ground VPIN2 = 2.7V; RL = 15K to Pin 8 CURRENT SENSE SECTION GV V3 SVR Ib Gain Maximum Input Signal Supply Voltage Rejection Input Bias Current Delay to Output OUTPUT SECTION IOL IOH tr tf Output Low Level Output High Level Rise Time Fall Time ISINK = 20mA ISINK = 200mA ISOURCE = 20mA ISOURCE = 200mA Tj = 25C Tj = 25C CL = 1nF (2) CL = 1nF (2) 13 12 0.1 1.5 13.5 13.5 50 50 150 150 0.4 2.2 13 12 0.1 1.5 13.5 13.5 50 50 150 150 0.4 2.2 V V V V ns ns (3 & 4) VPIN1 = 5V (3) 12 Vi 25V (3) 2.85 0.9 3 1 70 -2 150 -10 300 3.15 1.1 2.8 0.9 3 1 70 -2 150 -10 300 3.2 1.1 V/V V dB A ns 65 0.7 60 2 -0.5 5 Tj = 25C (6) 12 Vi 25V TMIN Tamb TMAX (2) VPIN4 Peak to Peak ERROR AMP SECTION VPIN1 = 2.5V 2.45 2.50 2.55 2.42 2.50 2.58 -0.3 90 1 70 6 -0.8 6 0.7 1.1 -1 65 0.7 60 2 -0.5 5 -0.3 90 1 70 6 -0.8 6 0.7 1.1 -2 V A dB MHz dB V mA V V 47 52 0.2 5 1.7 57 1 47 52 0.2 5 1.7 57 1 KHz % % V Tj = 25C Io = 1mA 12V Vi 25V 1 Io 20mA (Note 2) Line, Load, Temperature (2) 10Hz f 10KHz Tj = 25C (2) Tamb = 125C, 1000Hrs (2) -30 4.9 50 5 25 -30 4.95 5.00 5.05 4.90 5.00 5.10 6 6 0.2 20 25 0.4 5.1 4.82 50 5 25 6 6 0.2 20 25 0.4 5.18 V mV mV mV/C V V mV mA UC284X UC384X Uni t Min. T yp. Max. Min. Typ . Max.
-100 -180
-100 -180
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ELECTRICAL CHARACTERISTICS (continued)
Symbo l Parameter T est Cond ition s UC284X UC384X Min. T yp. Max. Min. T yp. Max. 15 7.8 9 7.0 16 8.4 10 7.6 17 9.0 11 8.2 14.5 7.8 8.5 7.0 16 8.4 10 7.6 17.5 9 11.5 8.2 Unit
UNDER-VOLTAGE LOCKOUT SECTION Start Threshold X842/4 X843/5 Min Operating Voltage After Turn-on X842/4 X843/5 PWM SECTION Maximum Duty Cycle X842/3 X844/5 Minimum Duty Cycle TOTAL STANDBY CURRENT Ist Ii V iz Start-up Current Operating Supply Current Zener Voltage VPIN2 = VPIN3 = 0V Ii = 25mA 0.5 11 34 1 20 0.5 11 34 1 20 mA mA V 93 46 97 48 100 50 0 93 47 97 48 100 50 0 % % % V V V V
N otes : 2. These parameters, although guaranteed, are not 100% tested in production. 3. Parameter measured at trip point of latch with VPIN2 = 0. 4. Gain defined as : VPIN1 A= ; 0 VPIN3 0.8 V VPIN3 5. Adjust V i above the start threshold before setting at 15 V. 6. Output frequency equals oscillator frequency for the UC3842 and UC3843. Output frequency is one half oscillator frequency for the UC3844 and UC3845.
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Figure 1 : Error Amp Configuration.
Error amp can source or sink up to 0.5mA
Figure 2 : Under Voltage Lockout.
During Under-Voltage Lockout, the output driver is biased to sink minor amounts of current. Pin 6 should be shunted to groundwith a bleederresistor Figure 3 : Current Sense Circuit .
to preventactivating the power switch with extraneous leakage currents.
Peak current (is) is determined by the formula 1.0 V IS max RS A small RC filter may be required to suppress switch transients.
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Figure 4.
Figure 5 : Deadtime vs. CT (RT > 5K).
for RT > 5K f =
1.72 RTCT
Figure 6 : Timing Resistance vs. Frequency.
Figure 7 : Output Saturation Characteristics.
Figure 8 : Error Amplifier Open-loop Frequency Response.
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Figure 9 : Open Loop Test Circuit.
High peak currents associatedwith capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close Figure 10 : Shutdown Techniques.
to pin 5 in a single point ground. The transistor and 5 K potentiometerareused to sampletheoscillator waveform and apply an adjustable ramp to pin 3.
Shutdown of the UC2842 can be accomplished by two methods; either raise pin 3 above1V or pull pin 1 below a voltage two diode drops above ground. Either method cause the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shut-
down conditionat pins 1 and/or3 is removed. In one example, an externally latched shutdown may be accomplishedby addingan SCR which will be reset by cyclingVi belowthe lowerUVLOthreshold.At this point the referenceturns off, allowing the SCR to reset.
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Figure 11 : Off-line Flyback Regulator.
Power Supply Specifications 1. Input Voltage : 95 VAC to 130 VAC (50 Hz/60 Hz) 2. Line Isolation : 3750 V 3. Switching Frequency : 40 KHz 4. Efficiency @ Full Load : 70 % Figure 12 : Slope Compensation.
5. Output Voltage : A. + 5 V, 5 % : 1 A to 4 A load Ripple voltage : 50 mV P-P Max. B. + 12 V, 3 % : 0.1 A to 0.3 A load Ripple voltage : 100 mV P-P Max. C. - 12 V, 3 % : 0.1 A to 0.3 A load Ripple voltage : 100 mV P-P Max.
A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50 %.
Note that capacitor, C, forms a filter with R2 to supress the leading edge switch spikes.
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mm MIN.. A a1 a2 b b1 C c1 D (1) E e e3 F (1) G L M S 3.8 4.6 0.4 8.55 5.8 1.27 7.62 4 5.3 1.27 0.68 8 (max.) 0.150 0.181 0.016 0.35 0.19 0.5 45 (typ.) 8.75 6.2 0.336 0.228 0.050 0.300 0.157 0.209 0.050 0.027 0.344 0.244 0.1 TYP. MAX.. MIN.. 1.75 0.25 1.6 0.46 0.25 0.014 0.007 0.020 0.004 inch TYP.. MAX.. 0.069 0.009 0.063 0.018 0.010
DIM.
OUTLINE AND MECHANICAL DATA
SO14
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
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mm MIN. A a1 B B1 b b1 D E e e3 e4 F I L Z 0.44 3.3 1.6 0.017 8.8 2.54 7.62 7.62 7.1 4.8 0.130 0.063 0.38 0.7 1.39 0.91 0.5 0.5 9.8 0.346 0.100 0.300 0.300 0.280 0.189 0.015 1.65 1.04 TYP. 3.3 0.028 0.055 0.036 0.020 0.020 0.386 0.065 0.041 MAX. MIN. inch TYP. 0.130 MAX.
DIM.
OUTLINE AND MECHANICAL DATA
Minidip 0.300"
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1998 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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